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» The Kernel Least-Mean-Square Algorithm
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70
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LCTRTS
2010
Springer
15 years 4 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
80
Voted
IEEEPACT
2009
IEEE
15 years 4 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
IISWC
2009
IEEE
15 years 4 months ago
SD-VBS: The San Diego Vision Benchmark Suite
—In the era of multi-core, computer vision has emerged as an exciting application area which promises to continue to drive the demand for both more powerful and more energy effi...
Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon,...
CLUSTER
2007
IEEE
15 years 4 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
CODES
2005
IEEE
15 years 3 months ago
CRAMES: compressed RAM for embedded systems
Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an e...
Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T...