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» The Observational Power of Clocks
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83
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ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
15 years 3 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
63
Voted
CDC
2009
IEEE
131views Control Systems» more  CDC 2009»
15 years 2 months ago
Dynamic clock calibration via temperature measurement
— We study a clock calibration problem for an ultra-low power timer on a sensor node platform. When the sensor is put into sleep mode, this timer is the only thing left running, ...
David I. Shuman, Mingyan Liu
PVLDB
2010
167views more  PVLDB 2010»
14 years 8 months ago
Runtime Measurements in the Cloud: Observing, Analyzing, and Reducing Variance
One of the main reasons why cloud computing has gained so much popularity is due to its ease of use and its ability to scale computing resources on demand. As a result, users can ...
Jörg Schad, Jens Dittrich, Jorge-Arnulfo Quia...
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
15 years 6 months ago
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jia...
ISLPED
1995
ACM
70views Hardware» more  ISLPED 1995»
15 years 1 months ago
Transformation and synthesis of FSMs for low-power gated-clock implementation
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
Luca Benini, Giovanni De Micheli