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» The Observational Power of Clocks
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BMCBI
2007
162views more  BMCBI 2007»
14 years 9 months ago
Three-Dimensional Phylogeny Explorer: Distinguishing paralogs, lateral transfer, and violation of "molecular clock" assumption w
Background: Construction and interpretation of phylogenetic trees has been a major research topic for understanding the evolution of genes. Increases in sequence data and complexi...
Namshin Kim, Christopher Lee
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 3 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
ICCD
2007
IEEE
106views Hardware» more  ICCD 2007»
15 years 1 months ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
Eric L. Hill, Mikko H. Lipasti
SLIP
2009
ACM
15 years 4 months ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya...