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DFT
2006
IEEE
122views VLSI» more  DFT 2006»
15 years 1 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
TVLSI
1998
99views more  TVLSI 1998»
14 years 9 months ago
Some experiments about wave pipelining on FPGA's
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
Eduardo I. Boemo, Sergio López-Buedo, Juan ...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 4 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 1 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
15 years 3 months ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...