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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 11 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
ASPLOS
2006
ACM
15 years 11 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
152
Voted
VL
2005
IEEE
113views Visual Languages» more  VL 2005»
15 years 10 months ago
Estimating the Numbers of End Users and End User Programmers
In 1995, Boehm predicted that by 2005, there would be “55 million performers” of “end user programming” in the United States. The original context and method which generat...
Christopher Scaffidi, Mary Shaw, Brad A. Myers
ECOOP
2005
Springer
15 years 10 months ago
Pitfalls in Unanticipated Dynamic Software Evolution
Abstract. The authors of this paper have all developed a framework that allows runtime adaptation of software systems. Based on our experiences, we wish to summarize common pitfall...
Peter Ebraert, Theo D'Hondt, Yves Vandewoude, Yola...
164
Voted
EMSOFT
2005
Springer
15 years 10 months ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee
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