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ASPLOS
2009
ACM
16 years 4 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos
ASPLOS
2009
ACM
16 years 4 months ago
StreamRay: a stream filtering architecture for coherent ray tracing
The wide availability of commodity graphics processors has made real-time graphics an intrinsic component of the human/computer interface. These graphics cores accelerate the z-bu...
Karthik Ramani, Christiaan P. Gribble, Al Davis
CCS
2009
ACM
16 years 4 months ago
Efficient IRM enforcement of history-based access control policies
Inlined Reference Monitor (IRM) is an established enforcement mechanism for history-based access control policies. IRM enforcement injects monitoring code into the binary of an un...
Fei Yan, Philip W. L. Fong
160
Voted
POPL
2010
ACM
16 years 1 months ago
Automatically Generating Instruction Selectors Using Declarative Machine Descriptions
Despite years of work on retargetable compilers, creating a good, reliable back end for an optimizing compiler still entails a lot of hard work. Moreover, a critical component of ...
João Dias, Norman Ramsey
118
Voted
CGO
2010
IEEE
15 years 10 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
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