Sciweavers

4498 search results - page 858 / 900
» The Power of Data
Sort
View
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
15 years 3 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
15 years 3 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
PPOPP
2006
ACM
15 years 3 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
SIGCOMM
2006
ACM
15 years 3 months ago
Algorithms to accelerate multiple regular expressions matching for deep packet inspection
There is a growing demand for network devices capable of examining the content of data packets in order to improve network security and provide application-specific services. Most...
Sailesh Kumar, Sarang Dharmapurikar, Fang Yu, Patr...
BROADNETS
2005
IEEE
15 years 3 months ago
Using location information for scheduling in 802.15.3 MAC
— In recent years, UWB has received much attention as a suitable Physical Layer (PHY) for Wireless Personal Area Networks (WPANS). UWB allows for low cost, low power, high bandwi...
Sethuram Balaji Kodeswaran, Anupam Joshi