A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
— Energy efficient operation is of paramount importance for battery-powered wireless nodes. In an effort to conserve energy, standard protocols for WLANs have the provision for w...
We propose a generic algorithmic model called STAMP (Synchronous, Transactional, and Asynchronous MultiProcessing) as a universal performance and power complexity model for multit...
ABSTRACT Motivated by data value locality and quality tolerance present in multimedia applications, we propose a new micro-architecture, Region-level Approximate Computation Buffer...