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137
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IPPS
2006
IEEE
15 years 11 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
CODES
2007
IEEE
15 years 11 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
153
Voted
CN
2007
168views more  CN 2007»
15 years 5 months ago
A MAC layer power management scheme for efficient energy delay tradeoff in a WLAN
— Energy efficient operation is of paramount importance for battery-powered wireless nodes. In an effort to conserve energy, standard protocols for WLANs have the provision for w...
Mahasweta Sarkar, Rene L. Cruz
IPPS
2007
IEEE
15 years 11 months ago
STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems
We propose a generic algorithmic model called STAMP (Synchronous, Transactional, and Asynchronous MultiProcessing) as a universal performance and power complexity model for multit...
Michel Dubois, Hyunyoung Lee, Lan Lin
ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
15 years 10 months ago
Region-level approximate computation reuse for power reduction in multimedia applications
ABSTRACT Motivated by data value locality and quality tolerance present in multimedia applications, we propose a new micro-architecture, Region-level Approximate Computation Buffer...
Xueqi Cheng, Michael S. Hsiao