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DAC
1996
ACM
15 years 8 months ago
Early Power Exploration - A World Wide Web Application
Abstract: Exploration at the earliest stages of the design process is an integral component of effective low-power design. Nevertheless, superficial high-level analyses with insuff...
David Lidsky, Jan M. Rabaey
CSREAESA
2006
15 years 5 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
JCP
2008
232views more  JCP 2008»
15 years 4 months ago
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira ...
TWC
2008
127views more  TWC 2008»
15 years 4 months ago
Distributed beamforming and power allocation for cooperative networks
Cooperative diversity systems rely on using relay nodes to relay copies of transmitted information to the destination such that each copy experiences different channel fading, henc...
Zhiguo Ding, Woon Hau Chin, Kin K. Leung
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 10 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...