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GLVLSI
2009
IEEE
151views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Reliability aware NoC router architecture using input channel buffer sharing
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Mohammad Hossein Neishaburi, Zeljko Zilic
130
Voted
JEC
2006
100views more  JEC 2006»
15 years 24 days ago
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications
During the last two decades, Single Instruction Multiple Data (SIMD) processors have become important architectures in embedded systems for image processing applications. The main ...
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Ba...
116
Voted
CASES
2006
ACM
15 years 6 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
ICN
2001
Springer
15 years 5 months ago
Evaluation of an Algorithm for Dynamic Resource Distribution in a Differentiated Services Network
New applications have been introduced to the today’s “best-effort” IP networks having different bandwidth and delay guarantee requirements. The IETF is currently focused on D...
Eugenia G. Nikolouzou, Petros Sampatakos, Iakovos ...
123
Voted
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 7 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...