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    DATE
    2002
    IEEE
    89views Hardware» more  DATE 2002»
    Sizing Power/Ground Meshes for Clocking and Computing Circuit Components
    15 years 2 months ago
    Sizing Power/Ground Meshes for Clocking and Computing Circuit Components
    Download  www.date-conference.com
    Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malg...
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    ISLPED
    1998
    ACM
    75views Hardware» more  ISLPED 1998»
    A power optimization method considering glitch reduction by gate sizing
    15 years 1 months ago
    A power optimization method considering glitch reduction by gate sizing
    Download  www.cecs.uci.edu
    Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
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    ICCAD
    1993
    IEEE
    101views Hardware» more  ICCAD 1993»
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
    15 years 1 months ago
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
    Download  www.eecg.utoronto.ca
    Kerry S. Lowe, P. Glenn Gulak
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    ICCAD
    1995
    IEEE
    79views Hardware» more  ICCAD 1995»
    Optimal wire sizing and buffer insertion for low power and a generalized delay model
    15 years 1 months ago
    Optimal wire sizing and buffer insertion for low power and a generalized delay model
    Download  www.cs.uic.edu
    John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
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    ASPDAC
    2010
    ACM
    107views Hardware» more  ASPDAC 2010»
    Buffered clock tree sizing for skew minimization under power and thermal budgets
    14 years 7 months ago
    Buffered clock tree sizing for skew minimization under power and thermal budgets
    Download  www.asp-dac.itri.org.tw
    Krit Athikulwongse, Xin Zhao, Sung Kyu Lim
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