Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

48

ICCAD
1995
IEEE

favoriteEmaildiscussreport

79views Hardware» more ICCAD 1995»

Optimal wire sizing and buffer insertion for low power and a generalized delay model

15 years 1 months ago

Optimal wire sizing and buffer insertion for low power and a generalized delay model

Download www.cs.uic.edu

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin

Real-time Traffic

Hardware | ICCAD 1995 |

claim paper

Related Content

» Discrete Buffer and Wire Sizing for LinkBased NonTree Clock Networks

» Interconnect Delay Minimization Using a Novel PreMidPost Buffer Strategy

» Optimum wire sizing of RLC interconnect with repeaters

» A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing

» An Onlogn time algorithm for optimal buffer insertion

» A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model

» Simultaneous driver and wire sizing for performance and power optimization

» Nonuniform clock mesh optimization with linear programming buffer insertion

» Practical repeater insertion for low power what repeater library do we need

Post Info
More Details (n/a)

Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	ICCAD
Authors	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin

Comments (0)