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» The Size of Power Automata
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DAC
1996
ACM
15 years 4 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
CODES
2001
IEEE
15 years 3 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
TVLSI
2008
74views more  TVLSI 2008»
14 years 11 months ago
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
LICS
1998
IEEE
15 years 3 months ago
Compositional Analysis of Expected Delays in Networks of Probabilistic I/O Automata
Probabilistic I/O automata (PIOA) constitute a model for distributed or concurrent systems that incorporates a notion of probabilistic choice. The PIOA model provides a notion of ...
Eugene W. Stark, Scott A. Smolka
WOLLIC
2009
Springer
15 years 6 months ago
Property Driven Three-Valued Model Checking on Hybrid Automata
Abstract. In this paper, we present a three-valued property driven model checking algorithm for the logic CTL on hybrid automata. The technique of multivalued model checking for hy...
Kerstin Bauer, Raffaella Gentilini, Klaus Schneide...