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ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 4 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
USENIX
2004
15 years 1 months ago
Making the "Box" Transparent: System Call Performance as a First-Class Result
For operating system intensive applications, the ability of designers to understand system call performance behavior is essential to achieving high performance. Conventional perfo...
Yaoping Ruan, Vivek S. Pai
AAAI
1994
15 years 1 months ago
Parsing Embedded Clauses with Distributed Neural Networks
A distributed neural network model called SPEC for processing sentences with recursive relative clauses is described. The model is based on separating the tasks of segmenting the ...
Risto Miikkulainen, Dennis Bijwaard
CASCON
1996
148views Education» more  CASCON 1996»
15 years 1 months ago
Reuse in the application layer
Today's advanced CASE tools, combining the building-block and generative approaches to software reuse, are effective for reuse of software components and procedures in the pr...
Hirotomo Okuno, Hideki Matsumoto, Hironori Asai, M...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 11 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...