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HPCA
2012
IEEE
14 years 18 days ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
JCM
2008
118views more  JCM 2008»
15 years 5 months ago
New Receiver Architecture Based on Optical Parallel Interference Cancellation for the Optical CDMA
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
N. Elfadel, A. A. Aziz, E. Idriss, A. Mohammed, N....
CF
2009
ACM
15 years 11 months ago
Scheduling dynamic parallelism on accelerators
Resource management on accelerator based systems is complicated by the disjoint nature of the main CPU and accelerator, which involves separate memory hierarhcies, different degr...
Filip Blagojevic, Costin Iancu, Katherine A. Yelic...
160
Voted
USENIX
1996
15 years 6 months ago
Transparent Fault Tolerance for Parallel Applications on Networks of Workstations
This paper describes a new method for providingtransparent fault tolerance for parallel applications on a network of workstations. We have designed our method in the context of sh...
Daniel J. Scales, Monica S. Lam
IPPS
1997
IEEE
15 years 9 months ago
A Tool for On-line Visualization and Interactive Steering of Parallel HPC Applications
Tools for parallel systems today range from specification over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
Sabine Rathmayer