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ITC
1996
IEEE
99views Hardware» more  ITC 1996»
15 years 10 months ago
Detecting Delay Flaws by Very-Low-Voltage Testing
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
Jonathan T.-Y. Chang, Edward J. McCluskey
ET
2002
97views more  ET 2002»
15 years 5 months ago
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
168
Voted
ET
2002
105views more  ET 2002»
15 years 5 months ago
An Integrated Framework for the Design and Optimization of SOC Test Solutions
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for...
Erik Larsson, Zebo Peng
KBSE
2009
IEEE
16 years 16 days ago
ReAssert: Suggesting Repairs for Broken Unit Tests
—Developers often change software in ways that cause tests to fail. When this occurs, developers must determine whether failures are caused by errors in the code under test or in...
Brett Daniel, Vilas Jagannath, Danny Dig, Darko Ma...
ATS
2003
IEEE
75views Hardware» more  ATS 2003»
15 years 11 months ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer