193 search results - page 13 / 39 » The TigerSHARC DSP Architecture |
LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
VLSID
2002
IEEE
15 years 11 months ago
2002
IEEE
114
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LCTRTS
1999
Springer
15 years 3 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
104
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ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
74
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IPPS
2007
IEEE
15 years 5 months ago
2007
IEEE
DSP applications can be suitably represented using Process Network Models. This paper uses a modification of Kahn Process Network to solve the problem of finding an optimum arch...