193 search results - page 8 / 39 » The TigerSHARC DSP Architecture |
MJ
2006
14 years 11 months ago
2006
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
ICASSP
2011
IEEE
14 years 2 months ago
2011
IEEE
—Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two...
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CVPR
2007
IEEE
14 years 11 months ago
2007
IEEE
Considerable research work has been done in the area of surveillance and biometrics, where the goals have always been high performance, robustness in security and cost optimizatio...
ISSS
1999
IEEE
15 years 3 months ago
1999
IEEE
The Motorola System on Chip Design Technologies (SoCDT) team aims at providing a system design environment for its customers. The Toulouse branch concentrates on design efforts in...
DAC
1997
ACM
15 years 3 months ago
1997
ACM
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...