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VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
15 years 10 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
ISPASS
2006
IEEE
15 years 3 months ago
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures
The present work presents a cycle-level execution-driven simulator for modern GPU architectures. We discuss the simulation model used for our GPU simulator, based in the concept o...
Victor Moya Del Barrio, Carlos González, Jo...
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
14 years 7 months ago
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
Christophe Dubach, Timothy M. Jones, Edwin V. Boni...
EDOC
2008
IEEE
15 years 4 months ago
Augmenting the Zachman Enterprise Architecture Framework with a Systemic Conceptualization
The Zachman Framework offers a classification of the models created in an enterprise architecture project. These models form a holistic representation of the organization. Despite...
Alain Wegmann, Anders Kotsalainen, Lionel Matthey,...
FIDJI
2003
Springer
15 years 3 months ago
Hard Real-Time Implementation of Embedded Software in JAVA
The popular slogan ”write once, run anywhere” effectively renders the expressive capabilities of the Java programming framework for developing, deploying, and reusing target-i...
Jean-Pierre Talpin, Abdoulaye Gamatié, Davi...