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VLSID
2008
IEEE
95views VLSI» more  VLSID 2008»
15 years 10 months ago
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
Biswajit Ray, Santanu Mahapatra
NCA
2007
IEEE
15 years 4 months ago
Dynamic load balancing for network intrusion detection systems based on distributed architectures
Increasing traffic and the necessity of stateful analyses impose strong computational requirements on network intrusion detection systems (NIDS), and motivate the need of distrib...
Mauro Andreolini, Sara Casolari, Michele Colajanni...
DAC
1997
ACM
15 years 2 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
DSVIS
2005
Springer
15 years 3 months ago
A Calculus for the Refinement and Evolution of Multi-user Mobile Applications
The calculus outlined in this paper provides a formal architectural framework for describing and reasoning about the properties of multi-user and mobile distributed interactive sys...
W. Greg Phillips, T. C. Nicholas Graham, Christoph...
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
15 years 10 months ago
Timing Yield Calculation Using an Impulse-Train Approach
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
Srinath R. Naidu