265 search results - page 2 / 53 » The Use of Genetic Algorithm to Reduce Power Consumption dur... |
CEC
2005
IEEE
13 years 12 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
ENGL
2007
13 years 6 months ago
2007
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
ICC
2009
IEEE
14 years 29 days ago
2009
IEEE
—According to several studies, the power consumption of the Internet accounts for up to 10% of the worldwide energy consumption, and several initiatives are being put into place ...
DATE
2008
IEEE
14 years 21 days ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...