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» The amorphous FPGA architecture
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FPL
2008
Springer
91views Hardware» more  FPL 2008»
14 years 11 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
ARC
2011
Springer
198views Hardware» more  ARC 2011»
14 years 1 months ago
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security
Increasing transmission speeds in high-performance networks pose significant challenges to protecting the systems and networking infrastructure. Reconfigurable devices have alrea...
Sascha Mühlbach, Andreas Koch
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
15 years 1 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
AHS
2006
IEEE
133views Hardware» more  AHS 2006»
15 years 3 months ago
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
Justin Lee, Joaquin Sitte
SLIP
2006
ACM
15 years 3 months ago
The routability of multiprocessor network topologies in FPGAs
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...
Manuel Saldaña, Lesley Shannon, Paul Chow