862 search results - page 61 / 173 » The amorphous FPGA architecture |
ASAP
2002
IEEE
15 years 2 months ago
2002
IEEE
† Introducing FPGA components into DSP system implementations creates an assortment of challenges across system architecture and logic design. Recognizing that some of the greate...
DSD
2009
IEEE
14 years 7 months ago
2009
IEEE
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper proposes a novel architecture supporting dynamic load balancing on an FPGA for a Molecular Dynamics algorithm. Load balancing is primarily achieved through the use of s...
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AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is d...
ASAP
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...