3192 search results - page 504 / 639 » The minimum latency problem |
116
Voted
ICCD
2001
IEEE
15 years 9 months ago
2001
IEEE
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
15 years 9 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
106
Voted
ICCAD
2001
IEEE
15 years 9 months ago
2001
IEEE
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. Certain devic...
129
Voted
CVPR
2010
IEEE
15 years 9 months ago
2010
IEEE
Taking multiple exposures is a well-established approach both for capturing high dynamic range (HDR) scenes and for noise reduction. But what is the optimal set of photos to captur...
DAC
2009
ACM
15 years 7 months ago
2009
ACM
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...