Sciweavers

3 search results - page 1 / 1
» Thermal-Aware SoC Test Scheduling with Test Set Partitioning...
Sort
View
87
Voted
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
15 years 5 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
87
Voted
DSD
2009
IEEE
85views Hardware» more  DSD 2009»
15 years 5 months ago
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
Zhiyuan He, Zebo Peng, Petru Eles
92
Voted
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 5 months ago
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
Zhiyuan He, Zebo Peng, Petru Eles