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GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 5 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
SIPS
2006
IEEE
15 years 5 months ago
Architecture-Aware LDPC Code Design for Software Defined Radio
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of the...
Yuming Zhu, Chaitali Chakrabarti
GLOBECOM
2010
IEEE
14 years 10 months ago
Interference-Aware Robust Wireless Mesh Network Design
Interference has been proven to have an effect on the performance in wireless mesh networks (WMN). Using multichannels can improve the performance of WMNs by reducing interference ...
Farah Kandah, Weiyi Zhang, Yashaswi Singh, Juan Li
INFOCOM
2010
IEEE
14 years 10 months ago
Socially-Aware Network Design Games
—In many scenarios network design is not enforced by a central authority, but arises from the interactions of several self-interested agents. This is the case of the Internet, wh...
Jocelyne Elias, Fabio Martignon, Konstantin Avrach...