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IPPS
2005
IEEE
15 years 5 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
15 years 4 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
FOSAD
2009
Springer
15 years 3 months ago
Verification of Concurrent Programs with Chalice
A program verifier is a tool that allows developers to prove that their code satisfies its specification for every possible input and every thread schedule. These lecture notes des...
K. Rustan M. Leino, Peter Müller, Jan Smans
SOSP
2007
ACM
15 years 8 months ago
TxLinux: using and managing hardware transactional memory in an operating system
TxLinux is a variant of Linux that is the first operating system to use hardware transactional memory (HTM) as a synchronization primitive, and the first to manage HTM in the sc...
Christopher J. Rossbach, Owen S. Hofmann, Donald E...
IPPS
1996
IEEE
15 years 3 months ago
Dag-Consistent Distributed Shared Memory
We introduce dag consistency, a relaxed consistency model for distributed shared memory which is suitable for multithreaded programming. We have implemented dag consistency in sof...
Robert D. Blumofe, Matteo Frigo, Christopher F. Jo...