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152
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ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
15 years 9 months ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
114
Voted
HOST
2009
IEEE
15 years 8 months ago
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
Hardware Trojans in integrated circuits and systems have become serious concern to fabless semiconductor industry and government agencies in recent years. Most of the previously p...
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquel...
130
Voted
IPPS
2010
IEEE
15 years 2 months ago
Prototype for a large-scale static timing analyzer running on an IBM Blue Gene
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
Akintayo Holder, Christopher D. Carothers, Kerim K...
DAC
2009
ACM
16 years 6 months ago
Interconnection fabric design for tracing signals in post-silicon validation
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to ...
Xiao Liu, Qiang Xu
DAC
2009
ACM
16 years 6 months ago
On systematic illegal state identification for pseudo-functional testing
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
Feng Yuan, Qiang Xu