821 search results - page 27 / 165 » Time Dependent Processing in a Parallel Pipeline Architectur... |
ICIP
2009
IEEE
15 years 10 months ago
2009
IEEE
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
PARLE
1992
15 years 1 months ago
1992
Complex and data-intensive database queries mandate parallel processing strategies to achieve sufficiently short response times. In praxis, parallel database processing is mostly b...
IFIP
2001
Springer
15 years 2 months ago
2001
Springer
: A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture...
MVA
1992
14 years 11 months ago
1992
This paper presents the design of an ASIC intended for optimal edge detection of blurred and noisy 2-D images. The chip has a parallel and pipelined architecture which processes a...
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FPGA
2009
ACM
15 years 2 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...