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ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
15 years 4 months ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
CODES
2006
IEEE
15 years 3 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
IPPS
2007
IEEE
15 years 4 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
RTI
2002
43views more  RTI 2002»
14 years 9 months ago
A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing
Joan Batlle, Joan Martí, Pere Ridao, Josep ...
HIPC
2005
Springer
15 years 3 months ago
Mobile Pipelines: Parallelizing Left-Looking Algorithms Using Navigational Programming
Abstract. Parallelizing a sequential algorithm—i.e., manually or automatically converting it into an equivalent parallel distributed algorithm—is an important problem. Ideally,...
Lei Pan, Ming Kin Lai, Michael B. Dillencourt, Lub...