112 views123 votes15 years 1 months ago CORR 2006»
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
180 views137 votes15 years 6 months ago WMPI 2004»
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
This paper offers a high-level retrospective overview of the GOPI middleware platform which is the outcome of a three year project aimed at the development of generic, configurabl...
119 views113 votes15 years 7 months ago ICPADS 2006»
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
160 views119 votes15 years 5 months ago ISHPC 2000»
This paper describes transparent mechanisms for emulating some of the data distribution facilities offered by traditional data-parallel programming models, such as High Performance...
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
This paper presents a distributed middleware architecture based on a service-oriented approach, to manage high volume sensor events. Event management takes a multi-step operation f...
203 views152 votes15 years 7 months ago PPOPP 2006»
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
122 views114 votes15 years 2 months ago WEBNET 1997»
: We are building an infrastructure for the platform-independent distribution and execution of high-performance mobile code as a future Internet technology to complement and perhap...
104 views120 votes15 years 7 months ago IFIP 2007»
Hybrid networks are networks capable of switching data at multiple levels (optical and IP packet level) by means of multi-service optical switches. As a result of that, huge flows...