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» Time Management in the DoD High Level Architecture
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ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
15 years 6 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 2 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
ICCAD
2000
IEEE
159views Hardware» more  ICCAD 2000»
15 years 2 months ago
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
Erik Lauwers, Georges G. E. Gielen
ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
15 years 3 months ago
Efficient Thermal Simulation for Run-Time Temperature Tracking and Management
As power density increases exponentially, run-time regulation of operating temperature by dynamic thermal management becomes imperative. This paper proposes a novel approach to re...
Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, ...
IPPS
2007
IEEE
15 years 3 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson