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» Time Management in the DoD High Level Architecture
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181 views 122 votes 15 years 5 months ago  DAC 1989»
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
129 views 144 votes 15 years 7 months ago  CCGRID 2005»
In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emp...
118 views 98 votes 15 years 7 months ago  POLICY 2007»
Obligation Policies specify management actions that must be performed when a particular kind of event occurs and certain conditions are satisfied. Large scale distributed systems...
136 views 129 votes 15 years 5 months ago  ISN 1994»
There is a common unjustified belief that OSI management technology, despite being very powerful, is difficult to implement because of the complexity of the underlying service/prot...
113 views 103 votes 15 years 6 months ago  GRID 2004»
One of the biggest obstacles in the wide-spread industrial take-up of Grid technology is the existence of a large amount of legacy code that is not accessible as Grid services. Th...
108 views 101 votes 16 years 2 months ago  DAC 2004»
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
101 views 115 votes 15 years 6 months ago  DATE 2002»
This paper presents a novel Energy-Aware Compilation (EAC) framework that can estimate and optimize energy consumption of a given code taking as input the architectural and techno...
159 views 103 votes 15 years 6 months ago  CISIS 2010»
—The SERSCIS project aims to support the use of interconnected systems of services in Critical Infrastructure (CI) applications. The problem of system interconnectedness is aptly...
116 views 114 votes 15 years 1 months ago  CORR 2006»
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
150 views 84 votes 15 years 5 months ago  DAC 1996»
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...