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» Time Management in the DoD High Level Architecture
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DAC
1996
ACM
15 years 1 months ago
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...
Val Popescu, Bill McNamara
DAC
1999
ACM
15 years 10 months ago
Soft Scheduling in High Level Synthesis
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
Jianwen Zhu, Daniel Gajski
SASO
2008
IEEE
15 years 4 months ago
MyP2PWorld: Highly Reproducible Application-Level Emulation of P2P Systems
In this paper, we describe an application-level emulator for P2P systems with a special focus on high reproducibility. We achieve reproduciblity by taking control over the schedul...
Roberto Roverso, Mohammed Al-Aggan, Amgad Naiem, A...
96
Voted
JUCS
2010
96views more  JUCS 2010»
14 years 8 months ago
Multi-Level Context Management and Inference Framework for Smart Telecommunication Services
: Telco operators and other players are searching for intelligent value-added services, i.e., communication applications that take advantage of the huge amount of user data availab...
Carlos Baladrón Zorita, Alejandro Cadenas, ...
IPPS
2000
IEEE
15 years 2 months ago
Controlling Distributed Shared Memory Consistency from High Level Programming Languages
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Yvon Jégou