In this paper, we propose new dominance relations that can speed up significantly the solution process of nonlinear constrained dynamic optimization problems in discrete time and...
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
We present an algorithm, called the offset tree, for learning in situations where a loss associated with different decisions is not known, but was randomly probed. The algorithm i...
We explore the average-case “Vickrey” cost of structures in a random setting: the Vickrey cost of a shortest path in a complete graph or digraph with random edge weights; the V...
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...