14382 search results - page 88 / 2877 » Time in Connectionist Models |
100
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DATE
2002
IEEE
15 years 6 months ago
2002
IEEE
To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The meth...
118
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CPE
2000
Springer
15 years 5 months ago
2000
Springer
Abstract. This paper presents TimeNET, a software tool for the modelling and performability evaluation using stochastic Petri nets. The tool has been designed especially for models...
RTSS
1998
IEEE
15 years 5 months ago
1998
IEEE
: The Time-Triggered (TT) model of computation is a model for the representation and analysis of the design of large hard real-time systems. Central to this model is the concept of...
102
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DAC
1996
ACM
15 years 5 months ago
1996
ACM
This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...
111
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ISPD
2003
ACM
15 years 6 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...