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ISORC
2007
IEEE
13 years 9 months ago
Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache
Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded so...
Raimund Kirner, Peter P. Puschner
RTAS
2006
IEEE
13 years 8 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
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RTSS
2006
IEEE
13 years 8 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller