Sciweavers

518 search results - page 53 / 104
» Time-Sharing Parallel Applications with Performance Isolatio...
Sort
View
HPCA
2000
IEEE
15 years 7 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
130
Voted
APPT
2005
Springer
15 years 8 months ago
Static Partitioning vs Dynamic Sharing of Resources in Simultaneous MultiThreading Microarchitectures
Simultaneous MultiThreading (SMT) achieves better system resource utilization and higher performance because it exploits ThreadLevel Parallelism (TLP) in addition to “conventiona...
Chen Liu, Jean-Luc Gaudiot
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
15 years 9 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...
ICPADS
2008
IEEE
15 years 9 months ago
A Cost-Aware Resource Exchange Mechanism for Load Management across Grids
Numerous Grids have been created during the last years. Most of these Grids work in isolation and with different utilisation levels. As the resource utilisation within a Grid has ...
Marcos Dias de Assunção, Rajkumar Bu...
HPDC
2007
IEEE
15 years 9 months ago
IDEA: : an infrastructure for detection-based adaptive consistency control in replicated services
In Internet-scale distributed systems, replicationbased scheme has been widely deployed to increase the availability and efficiency of services. Hence, consistency maintenance amo...
Yijun Lu, Ying Lu, Hong Jiang