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VLSID
2008
IEEE
133views VLSI» more  VLSID 2008»
16 years 5 months ago
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
IPPS
2007
IEEE
15 years 11 months ago
Linking Compilation and Visualization for Massively Parallel Programs
This paper presents a technique to visualize the communication pattern of a parallel application at different points during its execution. Unlike many existing tools that show the...
Alex K. Jones, Raymond R. Hoare, Joseph St. Onge, ...
ICDM
2002
IEEE
156views Data Mining» more  ICDM 2002»
15 years 9 months ago
Predicting Rare Events In Temporal Domains
Temporal data mining aims at finding patterns in historical data. Our work proposes an approach to extract temporal patterns from data to predict the occurrence of target events,...
Ricardo Vilalta, Sheng Ma
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
15 years 9 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 9 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...