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» Timed Temporal Logics for Abstracting Transient States
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EMSOFT
2006
Springer
15 years 2 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
ICTAC
2009
Springer
14 years 8 months ago
A First-Order Policy Language for History-Based Transaction Monitoring
Online trading invariably involves dealings between strangers, so it is important for one party to be able to judge objectively the trustworthiness of the other. In such a setting,...
Andreas Bauer 0002, Rajeev Goré, Alwen Tiu
DSN
2008
IEEE
15 years 5 months ago
A characterization of instruction-level error derating and its implications for error detection
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which co...
Jeffrey J. Cook, Craig B. Zilles
ISCC
2007
IEEE
104views Communications» more  ISCC 2007»
15 years 4 months ago
Chronicle Recognition for Mobility Management Triggers
An optimally working mobile system requires tight cooperation and an information stream that flows impeccably between its components. This, however, is not the current state of t...
Christophe Dousson, Kostas Pentikousis, Tiia Sutin...
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...