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134
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CONIELECOMP
2011
IEEE
14 years 4 months ago
FPGA design and implementation for vertex extraction of polygonal shapes
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
Jorge Martínez-Carballido, Jorge Guevara-Es...
DAC
2011
ACM
14 years 17 days ago
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhr...
ICCAD
2006
IEEE
130views Hardware» more  ICCAD 2006»
15 years 9 months ago
On bounding the delay of a critical path
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
Leonard Lee, Li-C. Wang
112
Voted
ISCAS
2002
IEEE
108views Hardware» more  ISCAS 2002»
15 years 5 months ago
Optimal adaptive bandwidth monitoring for QoS based retrieval
—Network aware multimedia delivery applications are a class of applications that provide certain level of quality of service (QoS) guarantees to end users while not assuming unde...
Yinzhe Yu, Anup Basu, Irene Cheng
75
Voted
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
15 years 9 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow