395 search results - page 14 / 79 » Timed circuits: a new paradigm for high-speed design |
107
Voted
ITC
2003
IEEE
15 years 7 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
128
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ASPDAC
2008
ACM
15 years 3 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
105
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GLVLSI
2003
IEEE
15 years 7 months ago
2003
IEEE
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
107
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DFT
2006
IEEE
15 years 5 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
ASPDAC
2006
ACM
15 years 7 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...