395 search results - page 24 / 79 » Timed circuits: a new paradigm for high-speed design |
137
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VTS
2000
IEEE
15 years 6 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
137
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FPGA
2005
ACM
15 years 7 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
122
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ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
111
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DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...