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» Timed circuits: a new paradigm for high-speed design
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IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
15 years 5 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
IFIP
1999
Springer
15 years 4 months ago
Design Error Diagnosis in Digital Circuits without Error Model
We describe a new method for design error diagnosis in digital circuits, that doesn’t use any error model. A diagnostic specific pre-analysis of the circuit extracts a subcircui...
Raimund Ubar, Dominique Borrione
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
15 years 8 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
VLSID
2005
IEEE
223views VLSI» more  VLSID 2005»
16 years 2 days ago
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee...
IROS
2007
IEEE
134views Robotics» more  IROS 2007»
15 years 6 months ago
Design and control of a new active cardiac stabilizer
— Off-pump Coronary Artery Bypass Grafting (CABG) is probably an important milestone in the cardiac surgery history. This technique is currently made possible thanks to the use o...
Wael Bachta, Pierre Renaud, Edouard Laroche, Anton...