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» Timed circuits: a new paradigm for high-speed design
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TODAES
2002
134views more  TODAES 2002»
15 years 1 months ago
False-noise analysis using logic implications
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
Alexey Glebov, Sergey Gavrilov, David Blaauw, Vlad...
121
Voted
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
15 years 5 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
86
Voted
ISLPED
2007
ACM
57views Hardware» more  ISLPED 2007»
15 years 3 months ago
Resource area dilation to reduce power density in throughput servers
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
Michael D. Powell, T. N. Vijaykumar
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 7 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ADBIS
2005
Springer
138views Database» more  ADBIS 2005»
15 years 7 months ago
Software Quality and Life Cycles
Abstract. Quality of software has growing role of the modern software engineering work. Typical current trends in the development process are the dominating role of quality systems...
Hannu Jaakkola, Bernhard Thalheim