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» Timing Anomalies in Dynamically Scheduled Microprocessors
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IPPS
2007
IEEE
15 years 3 months ago
Determining the Minimum Energy Consumption using Dynamic Voltage and Frequency Scaling
While improving raw performance is of primary interest to most users of high-performance computers, energy consumption also is a critical concern. Some microprocessors allow volta...
Min Yeol Lim, Vincent W. Freeh
131
Voted
TCAD
2010
168views more  TCAD 2010»
14 years 4 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
72
Voted
ISCA
2002
IEEE
96views Hardware» more  ISCA 2002»
15 years 2 months ago
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste...
RTSS
2005
IEEE
15 years 3 months ago
Enhanced EDF Scheduling Algorithms for Orchestrating Network-Wide Active Measurements
Monitoring network status such as end-to-end delay, jitter, and available bandwidth is important to support QoS-sensitive applications and timely detection of network anomalies li...
Prasad Calyam, Chang-Gun Lee, Phani Kumar Arava, D...
92
Voted
SIGOPSE
1998
ACM
15 years 1 months ago
MMLite: a highly componentized system architecture
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
Johannes Helander, Alessandro Forin