93 search results - page 9 / 19 » Timing optimization of FPGA placements by logic replication |
FPGA
1997
ACM
15 years 1 months ago
1997
ACM
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
RTAS
2007
IEEE
15 years 3 months ago
2007
IEEE
The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area...
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IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
Replicating data objects onto servers across a system can alleviate access delays. The selection of data objects and servers requires solving a constraint optimization problem, wh...
DAC
1998
ACM
15 years 10 months ago
1998
ACM
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
DAGSTUHL
2006
14 years 11 months ago
2006
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...