188 search results - page 27 / 38 » Timing-driven optimization using lookahead logic circuits |
101
Voted
ICCAD
2007
IEEE
16 years 11 days ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
128
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TE
2010
14 years 10 months ago
2010
Abstract--As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used i...
127
Voted
FPGA
2000
ACM
15 years 7 months ago
2000
ACM
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
239
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GLVLSI
2011
IEEE
14 years 7 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
114
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...