188 search results - page 3 / 38 » Timing-driven optimization using lookahead logic circuits |
105
Voted
PDPTA
2003
15 years 2 months ago
2003
Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) carry propagation delay where n is the number of digits. Carry lookahead helps...
102
Voted
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
88
Voted
ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
117
Voted
ICCAD
1996
IEEE
15 years 5 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
110
Voted
ICCAD
2009
IEEE
14 years 11 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...