48 search results - page 4 / 10 » Tolerating data access latency with register preloading |
128
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EMSOFT
2005
Springer
15 years 6 months ago
2005
Springer
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely ...
207
Voted
MICRO
2000
IEEE
15 years 16 days ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
66
Voted
SC
2009
ACM
15 years 7 months ago
2009
ACM
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called “di...
113
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HPCA
2011
IEEE
14 years 4 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
68
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...